1.Comparing Design Hierarchies 比較golden 與 revised verilog
The WRITE HIER_COMPARE DOFILE command lets you write a dofile script that Conformal can use to compare two hierarchical designs. The dofile script verifies the two hierarchical designs starting at the lowest-level modules and progressing to the root module. At the end of the dofile, Conformal displays the total number of equivalent and non-equivalent modules.
The sample dofile below does the following:
-Reads in the two hierarchical designs
-Writes out the hierarchical dofile script
-Compares the design hierarchy
指令如下
read library golden.lib -verilog -golden read design golden.v -verilog -golden read library revised.lib -verilog -revised read design revised.v -verilog -revised write hier_compare dofile hier.do -replace set log file hier.log -replace dofile hier.do exit -force
2.Comparing Libraries 比較 standard cell .lib 與 verilog
In addition to comparing design hierarchies, the WRITE HIER_COMPARE DOFILE command compares two libraries, such as Liberty and Verilog libraries. The sample dofile below does the following:
-Reads in a synthesis library and simulation library
-Writes out all of the library models
-Compares the libraries
指令如下
read design syn.lib -liberty -golden read design simulation.v -verilog -revised write hier_compare dofile lib_ver.do -all -replace set log file lib_ver.log -replace dofile lib_ver.do exit -force
3. 檢查 netlist
lec -lpgxl -nogui read design Max_3.3V.cdl -spice -golden
4.自動化script
把要跑的指令寫到 lec.script
然後在terminal 執行
lec -nogui -dofile lec.script
